VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Rachmad Vidya Wicaksana Putra, Trio Adiono


Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for = 8, = 16, = 32 and = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

Full Text:



Biver, M., Kaeslin, H., & Tommasini, C., In-Place Updating of Path Metrics in Viterbi Decoders, IEEE Journal of Solid-State Circuits, 24(4), pp. 1158-1160, 1989.

Habib, I., Paker, Ö., & Sawitzki, S., Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(5), pp. 794-807, 2010.

Sugur, N.V., Siddamal, S.V., & Vemala, S.S., Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology, Proc. of 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, Mumbai, India, pp. 353-358, 2014.

He, J., Liu, H., Wang, Z., Huang, X., & Zhang, K., High-speed Low-Power Viterbi Decoder Design for TCM Decoders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), pp. 755-759, 2012.

Nargis, J., Vaithiyanathan, D., & Seshasayanan, R., Design of High Speed Low Power Viterbi Decoder for TCM System, Proc. of International Conference on Information Communication and Embedded Systems, Chennai, India, pp. 185-190, 2013.

Chakraborty, D., Raha, P., Bhattacharya, A., & Dutta, R., Speed Optimization of a FPGA based Modified Viterbi Decoder, Proc. of International Conference on Computer Communication and Informatics, Coimbatore, India, pp. 1-6, 2013.

Sun, F., & Zhang, T., Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder, IEEE Transactions on Circuits and Systems, 54(5), pp. 1060-1068, 2007.

Shiau, Y.H., Yang, H.Y., Chen, P.Y., & Huang, S.G., Power-Efficient Decoder Implementation based on State Transparent Convolutional Codes, IET Circuits, Devices & Systems, 6(4), pp. 227-234, 2012.

Azhar, M.W., Själander, M., Ali, H., Vijayashekar, A., Hoang, T.T., Ansari, K.K., & Larsson-Edefors, P., Viterbi Accelerator for Embedded Processor Datapaths, Proc. of IEEE 23rd International Conference on Application-Specific Systems, Architectures, and Processors, Delft, Netherlands, pp. 133-140, 2012.

Karim, M.U., Khan, M.U.K., & Khawaja, Y.M., An Area Reduced, Speed Optimized Implementation of Viterbi Decoder, Proc. of International Conference on Computer Networks and Information Technology, Abbottabad, Pakistan, pp. 93-98, 2011.

Kim, S., & Hwang, S.Y., Area-Efficient VLSI Architecture for the Traceback Viterbi Decoder Supporting Punctured Codes, Electronics Letters, 32(8), pp. 733-735, 1996.

Sparsoe, J., Jorgensen, H.N., Paaske, E., Pedersen, S., & Rubner-Petersen, T., An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures, IEEE Journal of Solid-State Circuits, 26(2), pp. 90-97, 1991.

Lloyd, A.H., Reynolds, M.R., & Shah, Y.C., VLSI Architectures for Viterbi Decoding, IEE Colloquium on VLSI Implementations for Second Generation Digital Cordless and Mobile Telecommunication Systems, London, United Kingdom, pp. 6/1-6/7, 1990.

Cabrera, C., Boo, M., & Bruguera, J.D., VLSI Implementation of an Area-Efficient Architecture for the Viterbi Algorithm, Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing, Munich, Germany, pp. 623-626, 1, 1997.

Bobby, N.D., Srivatsa, S.K., Kishore, L., Rajiv, A. & Suresh, S.S., Comparison of Fast Radix 2 ACS with Adaptive Fast Radix 2 ACS in Viterbi Decoder, Proc. of International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System, Tiruvannamalai, India, pp. 1-5, 2013.

Nandula, S., Rao, Y.S., & Embanath, S.P., High Speed Area Efficient Configurable Viterbi Decoder for WiFi and WiMAX Systems, Proc. of International Conference on Intelligent and Advanced Systems, Kuala Lumpur, Malaysia, pp. 1396-1399, 2007.

Putra, R.V.W., & Adiono, T., Hybrid Multi–System-on-Chip Architecture as a Rapid Development Approach for a High-Flexibility System, IEIE Transactions on Smart Processing and Computing, 5(1), pp. 55-62, 2016.

Putra, R.V.W., & Adiono, T., Hybrid Multi System-on-Chip Architecture: A Rapid Development Design for High-Flexibility System, Proc. of International Conference on Electronics Information and Communication, Danang, Vietnam, pp. 39-42, 2016.

Suganya, G.S., & Kavya, G., RTL Design and VLSI Implementation of an Efficient Convolutional Encoder and Adaptive Viterbi Decoder, Proc. of International Conference on Communications and Signal Processing, Melmaruvathur, India, pp. 494-498, 2013.

Kubota, S., Kato, S., & Ishitani, T., Novel Viterbi Decoder VLSI Implementation and Its Performance, IEEE Transactions on Communications, 41(8), pp. 1170-1178, 1993.

Wu, Z., Hou, S., & Li, H., A Light-weighted Viterbi Decoder Implemented in FPGA, Proc. of International Conference on Instrumentation Measurement Computer Communication and Control, Beijing, China, pp. 601-604, 2011.

Putra, R.V.W., Mareta, R., Anbarsanti, N., & Adiono, T., A New RTL Design Approach for DCT/IDCT-based Image Compression Architecture using the mCBE Algorithm, Journal of ICT Research and Applications, 6(2), pp. 131-150, 2012.

Putra, R.V.W., Mareta, R., Anbarsanti, N., & Adiono, T., The Efficient mCBE Algorithm and Quantization Numbers for Multiplierless and Low Complexity DCT/IDCT Image Compression Architecture, Proc. of International Conference on Electrical Engineering and Informatics, Bandung, Indonesia, pp. 1-6, 2011.

Putra, R.V.W., Adiono, T., The Refined mCBE Algorithm for Efficient Constants Multipliers Architecture, Proc. of International SoC Design Conference, Gyeongju, South Korea, pp. 129-130, 2015.

Guo, M., FPGA Design and Implementation of Systolic Array-Based Viterbi Decoders, Master Thesis, Department of Electrical and Computer Engineering, Concordia University, Montreal – Quebec – Canada, 2002.

Ramdani, A.Z., & Adiono, T., Dynamic States Viterbi Decoder Architecture Based on Systolic Array, Proc. of Regional Conference on Computer and Information Engineering, Yogyakarta, Indonesia, pp. 126-129, 2014.

DOI: http://dx.doi.org/10.5614%2Fitbj.ict.res.appl.2016.10.1.5


  • There are currently no refbacks.

Contact Information:

ITB Journal Publisher, LPPM – ITB, 

Center for Research and Community Services (CRCS) Building Floor 7th, 
Jl. Ganesha No. 10 Bandung 40132, Indonesia,

Tel. +62-22-86010080,

Fax.: +62-22-86010051;

e-mail: jictra@lppm.itb.ac.id.