DT-MSOF Strategy and its Application to Reduce the Number of Operations in AHP

Fazmah Arif Yulianto, Kuspriyanto Kuspriyanto, Teguh Nurhadi Suharsono


A computing strategy called Double Track–Most Significant Operation First (DT-MSOF) is proposed. The goal of this strategy is to reduce computation time by reducing the number of operations that need to be executed, while maintaining a correct final result. Executions are conducted on a sequence of computing operations that have previously been sorted based on significance. Computation will only run until the result meets the needs of the user. In this study, the DT-MSOF strategy was used to modify the Analytic Hierarchy Process (AHP) algorithm into MD-AHP in order to reduce the number of operations that need to be done. The conventional AHP uses a run-to-completion approach, in which decisions can only be obtained after all of the operations have been completed. On the other hand, the calculations in MD-AHP are carried out iteratively only until the conditions are reached where a decision can be made. The simulation results show that MD-AHP can reduce the number of operations that need to be done to obtain the same results (decisions) as obtained by conventional AHP. It was also found that the more uneven the distribution of priority values, the more the number of operations could be reduced.  


analytic hierarchy process; computational time; double-track; most significant operation first; operation reduction

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Yulianto, F.A. & Kuspriyanto, A New Approach to Reducing Execution Time in Real-Time Computation, in 5rd International Conference on Information and Communication Technology (ICoICT 2017), Malacca, Malaysia, 2017.

Yulianto, F.A., Kuspriyanto & Gondokaryono, Y.S., Computation Reduction for IRIS Process using DT-MSOF Method, International Journal on Electrical Engineering and Informatics, 10(1), pp. 140-152, Mar. 2018.

Saaty, R.W., The Analytic Hierarchy Process – What It Is and How It Is Used, Mathematical Modelling, 9(3), pp. 161-176, Jan. 1987.

Nielsen, A.M. & Kornerup, P., MSB-first Digit Serial Arithmetic, J.UCS The Journal of Universal Computer Science, 1(7), pp. 527-547, 1995.

Kuspriyanto & Kerlooza, Y.Y., Towards New Real-Time Processor: The Multioperand MSB-first Real-time Adder, in Euromicro Symposium on Digital System Design, 2004. DSD 2004, pp. 524-529, 2004.

Parhi, K K., An Improved Pipelined MSB-first Add-compare Select Unit Structure for Viterbi Decoders, IEEE Transactions on Circuits and Systems I: Regular Papers, 51(3), pp. 504-511, Mar. 2004.

Cheng, S.Y., Tang, C.K. & Lu, Y.C., An MSB-first 1-of-N Single-track Asynchronous Add-compare-select Unit for Viterbi Decoders, in 2009 International Conference on Communications, Circuits and Systems, pp. 361-364, 2009.

Li, B.M. & w Leong, P.H., FPGA-based MSB-first Bit-serial Variable Block Size Motion Estimation Processor, in 2006 IEEE International Conference on Field Programmable Technology, pp. 165-172, 2006.

Esmaeilzadeh, H., Sampson, A., Ceze, L. & Burger, D., Architecture Support for Disciplined Approximate Programming, in Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems, New York, NY, USA, pp. 301-312, 2012.

Khudia, D.S., Zamirai, B., Samadi, M. & Mahlke, S., Rumba: An Online Quality Management System for Approximate Computing, in 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), pp. 554-566, 2015.

Raha, A., Venkataramani, S., Raghunathan, V. & Raghunathan, A., Quality Configurable Reduce-And-Rank for Energy Efficient Approximate Computing, in 2015 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 665-670, 2015.

Chippa, V.K., Mohapatra, D., Roy, K., Chakradhar, S.T. & Raghunathan, A., Scalable Effort Hardware Design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(9), pp. 2004-2016, Sep. 2014.

Sidiroglou-Douskos, S., Misailovic, S., Hoffmann, H. & Rinard, M., Managing Performance vs. Accuracy Trade-offs with Loop Perforation, in Proceedings of the 19th ACM SIGSOFT Symposium and the 13th European Conference on Foundations of Software Engineering, New York, NY, USA, pp. 124-134, 2011.

Moore, R.E., Automatic Error Analysis in Digital Computation, Lockheed Aircraft Corporation, Missile and Space Division, Sunnyvale, California, LMSD-48421, Jan. 1959.

Moore, R.E., Interval Arithmetic and Automatic Error Analysis in Digital Computing, Stanford University, Stanford, California, 25, Nov. 1962.

Saaty, T.L., Decision Making with the Analytic Hierarchy Process, Int. J. Services Sciences, 1(1), pp. 83-98, 2008.

Saaty, T.L. & Shang, J.S., An Innovative Orders-of-magnitude Approach to AHP-based Multi-criteria Decision Making: Prioritizing Divergent Intangible Humane Acts, European Journal of Operational Research, 214(3), pp. 703-715, Nov. 2011.

Ergu, D., Kou, G., Peng, Y. & Shi, Y., A Simple Method to Improve the Consistency Ratio of the Pair-wise Comparison Matrix in ANP, European Journal of Operational Research, 213(1), pp. 246-259, Aug. 2011.

Kou, G., Ergu, D. & Shang, J., Enhancing Data Consistency in Decision Matrix: Adapting Hadamard Model to Mitigate Judgment Contradiction, European Journal of Operational Research, 236(1), pp. 261-271, Jul. 2014.

Kou, G. & Lin, C., A Cosine Maximization Method for The Priority Vector Derivation in AHP, European Journal of Operational Research, 235(1), pp. 225-232, May 2014.

Ho, W. & Ma, X., The State-of-the-art Integrations and Applications of the Analytic Hierarchy Process, European Journal of Operational Research, 267(2), pp. 399-414, 2018.

DOI: http://dx.doi.org/10.5614%2Fitbj.ict.res.appl.2018.12.3.3


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