On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing

Authors

  • Darwin C. Mangca Microelectronics Laboratory, EECE Department, MSU??Iligan Institute of Technology, Andres Bonifacio Avenue, Tibanga, Iligan City 9200,
  • Olga Joy Gerasta Microelectronics Laboratory, EECE Department, MSU??Iligan Institute of Technology, Andres Bonifacio Avenue, Tibanga, Iligan City 9200,
  • Anne Lorraine Luna Analog Devices General Trias, Inc., Gateway Business Park, General Trias, Cavite 4107,
  • Xi Zhu University of Technology Sydney, 15 Broadway Ultimo NSW 2007,
  • Jefferson Abelo Hora Microelectronics Laboratory, EECE Department, MSU??Iligan Institute of Technology, Andres Bonifacio Avenue, Tibanga, Iligan City 9200,

DOI:

https://doi.org/10.5614/j.eng.technol.sci.2018.50.5.1

Keywords:

ADC, FPGA, histogram-based ADC, linearity testing, on-the-fly method

Abstract

This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption.

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References

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Published

2018-11-30

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Articles