A Low-Complexity and High-Throughput RTL Design of a BCH (15,7) Decoder
DOI:
https://doi.org/10.5614/itbj.ict.2012.6.2.2Abstract
The Bose, Chaudhuri and Hocquenghem (BCH) codes form a large class of powerful random-error correcting cyclic codes. However, the implementation of its decoder requires high-complexity computation resources with a huge number of sequential circuits. This paper presents a low-complexity register transfer level (RTL) circuit design of a BCH decoder. In accordance with the table relationship between the syndrome and the error bit position, we propose a circuit that is mostly occupied by combinational elements without any sequential evolvement. Therefore the designed system has a low complexity and high throughput properties. The implementation of the BCH (15,7)decoder on Virtex 5 FX70TFF1136 requires 77 look-up tables (LUTs) with the maximum throughput reaching 1.7 Gbps.
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References
Costello Jr., D.J., Hangenauer, J., Imai, H. & Wicker, S.B., Applications of Error Control Coding, IEEE Transactions on Information Theory, 44(6), pp. 2531-2560, Oct. 1998.
ETSI, Digital Video Broadcasting (DVB); Frame Structure Channel Coding and Modulation for A Second Generation Digital Terrestrial Television Broadcasting System (DVB-T2), European Std. ETSI EN 302 755, V1.1.1, Sept. 2009.
IEEE, Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems, IEEE Std. 802.16e-2005, Feb. 2006.
Lin, S. & Costello Jr., D.J., Error Control Coding, Prentice Hall, 2004.
Massey, J., Step By Step Decoding of The Bose Chaudhuri Hocquenghem Codes, IEEE Transactions on Information Theory, 11(4), pp. 580-585, Oct. 1965.
Szwaja, Z., On Step By Step Decoding of The BCH Binary Codes, IEEE Transactions on Information Theory, 13(2), pp.350-351, Apr. 1967
Wei, S.W. & Wei, C.H., A High Speed Real Time Binary BCH Decoder,IEEE Transactions on Circuits and Systems for Video Technology, 3(2), pp.138-147, April 1993.
Massey, J.L., Shift-Register Synthesis and BCH Decoding, IEEE Transactions on Information Theory, 15(1), pp. 122-127, Jan.1969.
Hong, J. & Vetterli, M., Simple Algorithms for BCH Decoding, IEEE Transactions on Communications, 43(8), pp. 2324-2333, Aug. 1995.
Carter, N., Schaum's Outlines of Theory and Problems of Computer Architecture, Indian Special Edition, McGraw Hill, 2002.
Kumar, A. & Sawitzki, S., High-Throughput and Low-Power Architectures for Reed Solomon Decoder, Proc. of IEEE 39th Asilomar Conference on Signal, Systems, and Computers, pp.990-994, Nov. 2005.
