Performance Evaluation of Nanoscale Single- and Dual-Gate MESFETs Using COMSOL Multiphysics
DOI:
https://doi.org/10.5614/itbj.ict.res.appl.2026.20.1.4Keywords:
COMSOL multiphysics, dual-gate MESFET, electrostatic control, GaAs MESFET, leakage current, nanoscale transistorAbstract
In this work, a comparative numerical simulation of single-gate and double-gate depletion mode GaAs MESFETs in the nanometer domain using COMSOL Multiphysics was carried out. The objective was to evaluate the significance of multi-gate structures based on electrostatic control capability in terms of performance improvement in Schottky gate MESFETs. Four models were considered, including a traditional single-gate model, an analogous double-gate model, and their corresponding reduced scale models. Comparisons were made in terms of the concentration of electrons and output response depending on the value of the gate bias voltage. There were almost no differences between the two models when scaled at the same dimensions. The reduced dual-gate device exhibited lower leakage current and superior channel control compared to its single-gate counterpart, particularly with higher drain bias applied. This suggests that while the dual-gate design may not be advantageous in all dimensions, it proves more effective when MESFET structures are aggressively scaled, indicating that dual-gate configurations are preferable for nanoscale GaAs MESFETs operating in regimes where electrostatic degradation is significant.
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Ghiasi, A., Nkenyereye, L., Hazzazi, F., et al. Designing Process and Analysis of a New SOI-MESFET Structure with Enhanced DC and RF Characteristics for High-Frequency and High-Power Applications, PLoS ONE; 19, e0301980, 2024.
Lv, L., Yu, J., Hu, M., Yin, S., Zhuge, F., Ma, Y. & Zhai, T., Design and Tailoring of Two-Dimensional Schottky, PN and Tunnelling Junctions for Electronics and Optoelectronics, Nanoscale, 13, pp. 6713-6751, 2021.
Pavlidis, S., Medwig, G., Thomas, M., Ultrawide-Bandgap Semiconductors for High-Frequency Devices, IEEE Microwave, 25, 68-79, 2024.
Nagel, L.W. & McAndrew, C.C., The Evolution of Transistor Models: Always Trying to Keep Up with the Evolution of Transistors, IEEE Solid-State Circuits Mag, 15, pp. 29-35, 2023.
Porala, J.K. & Foong Lim, W., Comparative Analysis on Nitride-Based High Electron Mobility Transistor (HEMT), Phys Scr, 100, 082001, 2025.
Santermans, S., Hellings, G., Heyns, M., et al., Unraveling the Impact of Nano-Scaling on Silicon Field-Effect Transistors for the Detection of Single-Molecules, Nanoscale, 15, pp. 2354-2368, 2023.
Qin, L., Li, C., Wei, Y., et al. Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review. IEEE Access, 11, pp. 14028-14042, 2023.
Watanabe, H., Quantum Confinement and Two-Dimensional Electron Gases in Silicon Nanosheet Channels, IEEE Electron Devices Rev, 2, pp. 291-317, 2025.
Kumar, A., Agarwal, S., Varshnay ,V., et al., Opto-VLSI Devices and Circuits for Biomedical and Healthcare Applications, 1st edn. Boca Raton: CRC Press. Epub ahead of print 21 July 2023. DOI: 10.1201/9781003431138.
Kumar, N., Kumar, P., Dixit, A., et al., Classical to Quantum Transport in Multi-Dimensional Field Effect Transistors, 1st edn. Boca Raton: CRC Press. Epub ahead of print 16 September 2025. doi: 10.1201/9781003543923.
Gong, W., Cai, Z., Geng, S., et al. Scaling, Leakage Current Suppression, and Simulation of Carbon Nanotube Field-Effect Transistors, Nanomaterials, 15, 1168, 2025.
Chen, S., Wang, S., Liu, Z., et al. Channel and Contact Length Scaling of Two-Dimensional Transistors Using Composite Metal Electrodes, Nat Electron, 8(5), pp. 394-402, 2025.
Biswas, R. &Alam, M., Modeling Nanoscale Depletion Mode MESFET and Comparative Study for Different Semiconductor Materials. IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO). Kottayam, India: IEEE, pp. 1-6, 2022.
Hannah Blessy, P., Shenbagavalli, A. & Arun Samuel, T.S., A Comprehensive Review on the Single Gate, Double Gate, Tri-Gate, and Heterojunction Tunnel FET for Future Generation Devices, Silicon, 15, pp.2385-2405, 2023.
Zhang, L., Dang, W., Lu, Y. &Wang, Y., Design and Fabrication of 4 Double Input NAND Gate Chip with Excellent Electrical and Physical Performances, Sci Rep., 15, 29430, 2025.
Samanta, S., Gaas-Based Resonant Tunneling Diode: Device Aspects from Design, Manufacturing, Characterization and Applications, J Semicond, 44(10), 103101, 2023.


